6 - LISTE CPU INTEL (Core 2 Duo et QuadCore)

(Pour la liste complète : http://users.erols.com/chare/current_cpus.htm )

Cette liste donne des informations générales sur les CPU.

Core 2 (Socket 775)
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Celeron D-420 MMX SSE SSE2 SSE3
(Millville)
(EM64T, NX bit)
June 3, 2007 - {$39}		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die shared L2 (2-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Celeron D-430 MMX SSE SSE2 SSE3
(Millville)
(EM64T, NX bit)
June 3, 2007 - {$49}		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die shared L2 (2-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Celeron D-440 MMX SSE SSE2 SSE3
(Millville)
(EM64T, NX bit)
June 3, 2007 - {$59}		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die shared L2 (2-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Celeron D-4?? MMX SSE SSE2 SSE3
(Millville)
(EM64T, NX bit)
2008?		 775 balls
?MHz (200x?)
(64-bit quad-pumped bus)
?v		 Socket 775 32KB data (8-way)
32KB instruction (8-way)
512KB on-Die shared L2 (2-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Celeron-E1200 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
January 7, 2008		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Pentium-E2140 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2007 - {$74}		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Pentium-E2160 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2007 - {$84}		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Pentium-E2180 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
August 27, 2007 - {$84}		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Pentium-E2200 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
December, 2007 - {$84}		 775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Pentium-E2220 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
March 6, 2008		 775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Core 2 Duo-E4300 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
January 7, 2007 - ($183}		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E4400 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
April 22, 2007 - {$133}		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E4500 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
July 16, 2007		 775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E4600 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
October 22, 2007		 775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E4700 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
March 6, 2008		 775 balls
2600MHz (200x13)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6300 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($183}		 775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6320 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
April 22, 2007 - {$163}		 775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6400 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($224}		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6420 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
April 22, 2007 - {$183}		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6540 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 16, 2007		 775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6550 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$163}		 775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6600 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($316}		 775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6700 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($530}		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6750 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$183}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6850 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$266}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E6??? MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
2008?		 775 balls
?MHz (266x?)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Duo-E4200 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T)
2008?		 775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 167 million
0.065µm process
111mm² die
Core 2 Duo-E4300 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T)
2008?		 775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 167 million
0.065µm process
111mm² die
Core 2 Duo-E4400 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T)
2008?		 775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 167 million
0.065µm process
111mm² die
Core 2 Duo-E4??? MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T)
2008?		 775 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)
* 64GB cacheable		 167 million
0.065µm process
111mm² die
Core 2 Duo-E8190 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
January 7, 2008 - {$163}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)
* 64GB cacheable		 410 million
0.045µm process
107mm² die
Core 2 Duo-E8200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$163}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)
* 64GB cacheable		 410 million
0.045µm process
107mm² die
Core 2 Duo-E8400 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$183}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)
* 64GB cacheable		 410 million
0.045µm process
107mm² die
Core 2 Duo-E8500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$266}		 775 balls
3166MHz (333x9.5)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)
* 64GB cacheable		 410 million
0.045µm process
107mm² die
Core 2 Duo-??? MMX SSE SSE2 SSE3 SSE4
(Ridgefield)
(dual core, EM64T, NX bit, VT)
2008?		 775 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)
* 64GB cacheable		 ? million
0.045µm process
?mm² die
Intel
Processors		 Natural
State		 Sockets L1/L2 Cache
(Associativity)		 Transistors
Core 2 Extreme X6800 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - {$999}		 775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
1.2v		 Socket 775 2x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)
* 64GB cacheable		 291 million
0.065µm process
143mm² die
Core 2 Quad-Q6400 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Quad-Q6600 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
January 8, 2007 - {$851}		 775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Quad-Q6700 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
July 16, 2007 - {$530}		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Extreme-QX6700 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
November 14, 2006 - {$999}		 775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Extreme-QX6800 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
April 9, 2006 - {$1199}		 775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Extreme-QX6850 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
July 16, 2007 - {$999}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Extreme-QX6??? MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 775 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)
* 64GB cacheable		 ? million
0.065µm process
?mm² die
Core 2 Quad-Q9300 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$266}		 775 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Quad-Q9450 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$316}		 775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Quad-Q9550 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$530}		 775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Extreme-QX9650 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$999}		 775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Extreme-QX9770 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
March 24, 2008 - {$1399}		 775 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Extreme-??? MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 775 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Extreme-QX9775 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
February 19, 2008 - {$1499}		 771 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die unified L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Extreme-QX???? MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
2008?		 771 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 771 4x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die unified L2 (24-way)
* 64GB cacheable		 820 million
0.045µm process
?mm² die
Core 2 Extreme-QX???? MMX SSE SSE2 SSE3 SSE4
( ? )
(quad core, EM64T, NX bit, VT)
2008?		 775 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		 Socket 775 4x 32KB data (8-way)
4x 32KB instruction (8-way)
4x ?MB on-Die unified L2 (?-way)
* 64GB cacheable		 ? million
0.045µm process
?mm² die